1. Technical Field
The technical field relates to a digital-to-analog converter (DAC), and more particularly to a method and an apparatus for evaluating weighting of elements of the DAC, and a successive-approximated register analog-to-digital converter (SAR ADC) using the same.
2. Related Art
In recent years, integrated circuit design has been trending towards increasingly difficult demands on lowering power consumption and cost along with enhancing higher performance. In the design of front-end analog circuits, an efficient analog-to-digital converter (ADC) can drastically enhance the overall system performance. The ADC is responsible for converting the received analog signals into digital signals, and providing the digital signals for the operation of the back-end digital signal processing unit. Therefore, characteristics of the ADC such as its dynamic range, resolution, accuracy, linearity, sampling speed, power consumption, and its input stage are crucial factors which influence the overall system performance, and these characteristics serve as several parameters for evaluating the performance of the ADC.
For two categories in resolution and sampling speed, the application range of an ADC with 8-14 bits and one to several hundred mega samples per second (MSPS) is quite broad. Applications such as in the front-end of the base frequency or the intermediate frequency of a communication system, a biomedical imaging process such as the front-end of a ultrasonic imaging system, and the front-end of a laser array system are all within the range of applications. The ADC has many types of configurations, and when manufacturing an ADC matching the aforementioned specifications, a diverse array of configurations can be chosen. The mainstream ADC applied commercially is the pipeline analog-to-digital converter, or the pipeline ADC. However, in recent years, articles in prominent international journals have gravitated towards the successive-approximated register analog-to-digital converter (SAR ADC) as a popular research direction, because the SAR ADC configuration almost does not require a direct current bias voltage. Since the SAR ADC requires a good amount of digital circuits for control and signal processing, when the manufacturing process enters the deep sub-micron, the chip area and the power consumption needed for a portion of the digital circuits can be effectively reduced. Accordingly, the SAR ADC is suitable for developing the intellectual property from a large scale system-on-chip (SoC). In many disclosures, the SAR ADC has lower consumption and smaller chip area when compared to the pipeline ADC with the same specification requirements. Therefore, the technical development of the SAR ADC framework has become an active field of research.
However, a major functional block exists in the SAR ADC configuration: the digital-to-analog converter (DAC), which directly influences the performance of the SAR ADC. Due to the strong necessity of matching among each of the composed elements in the DAC, such as the capacitor, the DAC takes up a significant portion of the overall chip area and the power consumption of the SAR ADC. Thus, when the DAC requires a larger area, the driving circuit of the DAC also requires a larger driving force, and this further increases the area and power consumption. Since the cost of digital circuits is low, if the matching requirement the DAC places on each of the composed elements can be reduced or eliminated by adopting processing techniques using digital circuits, the overall chip area and power consumption of the ADC can be lowered.
FIG. 1 is a block diagram of a SAR ADC. FIG. 2A is a simplified circuit diagram of a DAC and a comparator in a SAR ADC during a sampling phase. FIG. 2B is a Thenevin equivalent circuit diagram of the circuit depicted in FIG. 2A. FIG. 2C is a simplified circuit diagram of a DAC and a comparator in a SAR ADC during a conversion phase. FIG. 2D is a Thenevin equivalent circuit diagram of the circuit depicted in FIG. 2C. Please refer to FIGS. 1, 2A, 2B, 2C, and 2D. A SAR ADC 10 includes a DAC 12, a sample and hold circuit 14, a comparator 16, and a successive-approximated register logic (SAR logic) circuit 18. The DACs depicted in FIGS. 2A, 2B, 2C, and 2D are formed by N capacitors C0, C1, . . . , CN-1, and these capacitors have a capacitance of radix 2:Cn=2n*C. in which N is a positive integer greater than 1, and n is a positive integer greater than or equal to 0 and less than N. Therefore, as shown in FIG. 2D, after the successive approximation, the SAR logic circuit 18 transmits a N-bit control signal to the DAC 12, that is the last ADC digital output value ADCOUT, in which all of the bit values K0, K1, . . . , KN-1 of the control signal equals 0 or 1. However, the linearity of the ADC is directly affected by the difference between the actual value and the ideal value of the capacitor.
FIG. 3 is a diagram illustrating a typical conversion function of the SAR ADC depicted in FIG. 1. Please refer to FIG. 3. A circular dotted line 32 represents a condition referred to as a missing decision level, and this condition occurs when a plurality of different input voltages may exist, with no corresponding different digital output values or the same digital output values. Accordingly, a linear conversion curve cannot be obtained by digital compensation. A circular dotted line 34 represents another condition referred to as a missing code, and this condition occurs when two adjacent input voltages correspond to two digital output values of an extremely large numerical difference. However, a linear conversion curve can still be obtained by digital compensation. As shown in FIG. 3, the DAC in a conventional ADC has a capacitance of a power of 2. Therefore, the missing decision level condition is generated, and this condition cannot be compensated digitally.